Static random access memories (SRAM's) comprise static memory cells which are designed to operate as a data latch. The memory cells typically use access transistors to couple the memory cell to a pair of complementary bit lines. The memory cell access transistors are selectively activated using a word line signal. Sense amplifier circuitry is used to detect voltage differentials between the bit lines. A pair of cross-coupled pulldown transistors are typically connected to the access transistors and are used to latch data.
Different static memory cell integrated circuit layouts have been used, however, these cells either have asymmetrical current paths through the pulldown transistors or require two word lines. The asymmetrical memory cells tend to be both unstable and susceptible to process variables such as two dimensional encroachment. Memory cells which use two word lines are more electrically symmetrical, but require additional die area for the second word line.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory cell which has the stability of the dual word line memory cell while requiring die area similar to the single word line memory cell.